1. Field of the Invention
This invention relates to a layout method for a semiconductor integrated circuit device such as a VLSI, and more particularly to layout method for reducing the chip size of a semiconductor integrated circuit device. Such a layout method may be performed when the shapes of blocks formed on the chip are to be optimized, or when, after the completion of the layout process of a VLSI, the chip size is required to be further reduced.
2. Description of the Prior Art
In a semiconductor integrated circuit device such as a VLSI, generally, circuit elements are arranged in one or more blocks, and wirings for establishing electrical connections between the blocks and between terminals of the I/O cells and blocks are formed in the areas between the blocks. Hereinafter, such an area which is disposed between blocks or between the periphery of the I/O cells and a block and may be used as paths for wirings is referred to as "a wiring channel". An example of a layout method in which the block shape is optimize is disclosed by the inventor in copending U.S. patent application Ser. No. 07/340,750 filed Apr. 20, 1989 which is incorporated herein by reference. In this method, the block shape is approximated to be rectangular. Namely, it is supposed that each of the blocks is a rectangle having smooth or linear four sides (i.e., the sides of the block are linear, or are not irregular). Then, the block shape is optimized. Hereinafter, this method is referred to as "the first method".
Another layout method hereinafter, referred to as "the second method") is disclosed in Japanese patent publication (Kokai) No. SHO62(1987)-144,650. In the second method, cells each incorporating one or more circuit elements are arranged in single row to form a belt-like block, and the wiring density is averaged as much as possible by bending the belt-like block.
In the first method, the variation in wiring density in channels cannot be compensated, and therefore channels where the wiring density is low have blank portions which are not used for wiring. This causes a problem in that the chip size cannot be sufficiently reduced by the first method. On the other hand, the second method has a problem in that cells must be arranged in a single row and belt-like fashion, with the result that the second method cannot be used for optimizing the layout of a semiconductor integrated circuit device.